Decoder architecture

LDPC convolutional code (LDPCCC) has an inherent efficient pipelined decoding implementation and has been shown to achieve a much lower error floor compared with its block code counterpart. This software package implements the decoding for protograph-based LDPCCC. Protograph-based LDPCCC inherits not only the adtantages of LDPCCC but also the efficient implementation of QC-LDPC codes. The theoretical code properties can be found in D. Mitchell, A. E. Pusane, K. S. Zigangirov and D. J. Costello, "Asmptotically good LDPC convolutional codes based on protographs". The details on the high-throughput decoder implementation using FPGA can be found in Xu Chen, et al, "A 2.0 Gb/s high-throughput decoder for protograph-based LDPC convolutional codes", , IEEE Transactions on Circuits and Systems I, Vol. 60, No. 7, pp. 1857-1869, July, 2013, USA. The architecture is described as follows,

Simulator How to start   

Step 1: Parity-Check Matrix Setting The QC-LDPC base matrix is

Block row number:
Block column number:
Submatrix size:
Cyclic-shift indices:

Step 2: Parameter Setting
SNR starts from: dB
SNR ends at: dB
How many points to simulate:
Max number of decoding iterations:
BER limit:

The parity-check matrix of the LDPCCC is obtained as follows:

Protograph Matrix
(1) Unwrap               

(2) Copy and Permute


Note: the plot is fake data because LDPC decoder program is not allowed to run on the external server.

Please email me for the software.


Developed by Xu Chen